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W83194BR-63S
STEP-LESS CLOCK FOR SIS CHIPSET
W83194BR-63S Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. 02/Apr 1.0 Dates Version Version on Web n.a. 1.0 All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Main Contents
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date:Ocl. 2000 Revision 1.0
W83194BR-63S
1.0
GENERAL DESCRIPTION
The W83194BR-63S is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-63S provides 64 CPU/PCI frequencies which are selectable with smooth transitions by hardware or software. W83194BR-63S also provides 13 SDRAM clocks. The W83194BR-63S provides step-less frequency programming by controlling the VCO freq. and the programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-63S accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at 0~-0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA, PCI, CPU, DIMM) is not recommend.
2.0
* * * * * * * * * * * * * * * * * *
PRODUCT FEATURES
Supports Pentium II and Pentium !!! CPU with I2C. 3 CPU clocks (one free-running CPU clock) 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks 2 AGP clocks 2 REF clocks as 14.318MHz outputs < 250ps skew among CPU and SDRAM clocks < 250ps skew among PCI clocks Skew from CPU(earlier) to PCI clock 1 to 4ns, center 2.6ns. Smooth frequency switch with selections from 66 MHz to 200 MHz CPU Stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio Programmable skew for CPU to SDRAM and CPU to AGP clock outputs I2C 2-Wire serial interface and I2C read back 0~-0.25% or 0.5% spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes MODE pin for power Management and RESET# out when system hang One 48 MHz for USB & one 24_48 MHz for super I/O 48-pin SSOP package
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
3.0 PIN CONFIGURATION
Vdd REF1^/ &AGPSEL REF0^/ &FS3 Vss Xin Xout VddP PCICLK0^/ &FS1 PCICLK1^/ &FS2 PCICLK2^ PCICLK3^ PCICLK4 PCICLK5/RESET$ Vss VddAGP AGPCLK0/SEL24_48* AGPCLK1/Mode1* Vss Vss 48MHz/&FS0 24_48MHz/&Mode Vdd48 SDATA* SDCLK* * : pull-up 120K &: pull-down 120K ^ : double strength # :input active low $ :open drain 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddLCPU CPUCLK0 CPUCLK1 CPUCS_C2 Vss VddSD SDRAM 0 SDRAM 1 SDRAM 2 Vss SDRAM 3 SDRAM 4 SDRAM 5 VddSD SDRAM 6 SDRAM 7 Vss SDRAM 8/PD# SDRAM 9/SDRAM_STOP# Vss SDRAM 10/PCI_STOP# SDRAM11/CPU_STOP# SDRAM12 VddSD
4.0
PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low *Internal 120k pull-up
4.1 Crystal I/O
SYMBOL Xin Xout PIN 5 6 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally.
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
4.2 CPU, SDRAM, PCI ,AGP Clock Outputs
SYMBOL CPUCLK[0:1] PIN 47,46 I/O OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddLCPU. Stopped if CPU_STOP# is low. Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddLCPU. Stopped if CPU_STOP# is low and Register7 bit7=0. SDRAM clock outputs. Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, PD# input Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, SDRAM_STOP# input Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, PCI_STOP# input Pin21 &Mode=0, SDRAM clock outputs. Pin21 &Mode=1, CPU_STOP# input Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched Input. SEL24_48&=0, Pin 21 is 24MHz; SEL24_48&=1, Pin21 is 48MHz PCI clock during normal operation. (pin17 Mode1*=1) If pin17 Mode1*=0, RESET# (open drain, 4ms low active pulse when Watch Dog time out) Low skew (< 250ps) AGP clock output. Latched Input. SEL24#_48*=1, Pin 21 is 24MHz; SEL24_48*=0, Pin21 is 48MHz AGP clock outputs Latched Input. Mode1*=1, Pin 13 is PCICLK; Mode1*=0, Pin2 is RESET#
CPUCS_C2
45
OUT
SDRAM [ 0:7],12 SDRAM 8/PD# SDRAM9/ SDRAM_STOP# SDRAM 10/ PCI_STOP# SDRAM 11/ CPU_STOP# PCICLK0^/&FS1
42,41,40,38,37 ,36,34,33 31 30 28 27 8
OUT OUT OUT OUT OUT I/O
PCICLK1^/&FS2
9
I/O
PCICLK [2:4]^
10,11,12
I/O
PCICLK5/ RESET# AGPCLK0/ SEL24#_48* AGPCLK1/ Mode1*
13
I/O
16
I/O
17
OUT
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
4.3
I2C Control Interface
SYMBOL PIN 23 24 I/O I/O IN
2
FUNCTION Serial data of I C 2-wire control interface Serial clock of I2C 2-wire control interface
SDATA* SDCLK*
4.4 Fixed Frequency Outputs
SYMBOL REF0^ / &AGPSEL PIN 2 I/O I/O FUNCTION 14.318MHz reference clock. This REF output is the atched input for &AGPSEL at initial power up for H/W selecting the output frequency of AGP clocks. 14.318MHz reference clock. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24_48MHz / &Mode 21 I/O 24_48MHz output clock, selected by pin16. Latched Input. &Mode=0, Pin 27,28,30,31 are SDRAM clocks; &Mode=1, Pin27,28,29,31 are CPU_STOP#,SDRAM_STOP#,PCI_STOP#,PD# 48MHz / &FS0 20 I/O 48MHz output for USB during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks.
REF1 ^/ &FS3
3
I/O
4.5 Power Pins
SYMBOL Vdd VddAGP VddLCPU VddP VddSD Vdd48 Vss PIN 1 15 48 7 43,35,29,25 19 FUNCTION Power supply for Ref [0:1] crystal and core logic. Power supply for AGP output, 3.3V. Power supply for CPUCLK[0:3], either 2.5V or 3.3V. Power supply for PCICLK_F, PCICLK[0:4], 3.3V. Power supply for SDRAM[0:12], and CPU PLL core, nominal 3.3V. Power for 24 & 48MHz output buffers and fixed PLL core.
4,14,18,19,29,32,39, Circuit Ground. 44
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
5.0 FREQUENCY SELECTION BY HARDWARE
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO CPU SDRAM (MHz) (MHz) (MHz) 400 66.6 66.6 400 100 100 498 166 166 400 133.3 133.3 400 66.6 100 400 100 66.6 400 100 133 400 133.3 100 336 112 112 372 124 124 414 138 138 300 150 150 399.6 66.6 133 300 100 150 300 150 100 480 160 120 PCI (MHz) 33.3 33.3 31.25 33.3 33.3 33.3 33.3 33.3 33.6 31 34.5 30 33.3 30 30 30 AGPSEL=0 (MHz) 66.6 66.6 62.5 66.6 66.6 66.6 66.6 66.6 67.2 62 69 60 66.6 60 60 60 AGPSEL=1 (MHz) 50 50 50 50 50 50 50 50 56 46.5 51.8 50 50 50 50 48
6.0 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Bytes sequence order for I2C controller :
Clock Address A(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
Set R/W to 1 when Read back", the data sequence is as follows :
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
FREQUENCY BY SOFTWARE
VCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 400 400 498 400 400 400 400 400 336 372 414 300 400 300 300 480 420 432 333.2 388 408 416 420 428 412 420 424 428 412 420 424 432
CPU 66.6 100 166 133.3 66.6 100 100 133.3 112 124 138 150 66.6 100 150 160 70 72 83.3 97 102 104 105 107 103 105 106 107 103 105 106 108
SDRAM (MHz) 66.6 100 166 133.3 100 66.6 133 100 112 124 138 150 133.3 150 100 120 105 108 111.07 129.33 136 138.67 140 142.67 68.67 70 106 107 103 105 106 108
PCI (MHz) 33.3 33.3 31.25 33.3 33.3 33.3 33.3 33.3 33.6 31 34.5 30 33.3 30 30 30 35 36 33.3 32.335 34 34.665 35 35.665 34.335 35 35.335 35.665 34.335 35 35.335 36
AGPSEL=0 (MHz) 66.6 66.6 62.5 66.6 66.6 66.6 66.6 66.6 67.2 62 69 60 66.6 60 60 60 70 72 66.6 64.67 68 69.33 70 71.33 68.67 70 70.67 71.33 68.67 70 70.67 72
AGPSEL=1 (MHz) 50 50 50 50 50 50 50 50 56 46.5 51.8 50 50 50 50 48 52.5 54 55.5 48.5 51 52 52.5 53.5 51.5 52.5 53 53.5 51.5 52.5 53 54
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 (MHz) (MHz)
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
VCO CPU SDRAM PCI SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 (MHz) (MHz) (MHz) (MHz) 1 0 0 0 0 0 390 130 130 32.5 1 0 0 0 0 1 405 135 135 33.75 1 0 0 0 1 0 408 136 136 34 1 0 0 0 1 1 417 139 139 34.75 1 0 0 1 0 0 420 140 140 35 1 0 0 1 0 1 426 142 142 35.5 1 0 0 1 1 0 429 143 143 35.75 1 0 0 1 1 1 435 145 145 36.25 1 0 1 0 0 0 390 130 130 32.5 1 0 1 0 0 1 405 135 135 33.75 1 0 1 0 1 0 414 138 138 34.5 1 0 1 0 1 1 426 142 142 35.5 1 0 1 1 0 0 411 137 137 34.25 1 0 1 1 0 1 417 139 139 34.75 1 0 1 1 1 0 423 141 141 35.25 1 0 1 1 1 1 426 142 142 35.5 1 1 0 0 0 0 390 130 97.5 32.5 1 1 0 0 0 1 396 132 99 33 1 1 0 0 1 0 408 136 102 34 1 1 0 0 1 1 411 137 102.75 34.25 1 1 0 1 0 0 414 138 103.5 34.5 1 1 0 1 0 1 426 142 106.5 26.625 1 1 0 1 1 0 432 144 108 27 1 1 0 1 1 1 438 146 109.5 27.375 1 1 1 0 0 0 450 150 112.5 28.125 1 1 1 0 0 1 459 153 114.75 28.69 1 1 1 0 1 0 468 156 117 29.25 1 1 1 0 1 1 489 163 122.25 30.565 1 1 1 1 0 0 498 166 124.5 31.125 1 1 1 1 0 1 525 175 131.25 32.815 1 1 1 1 1 0 534 178 133.5 33.375 1 1 1 1 1 1 549 183 137.25 34.315
AGP0 (MHz) 65 67.5 68 69.5 70 71 71.5 72.5 65 67.5 69 71 68.5 69.5 70.5 71 65 66 68 68.5 69 53.25 54 54.75 56.25 57.38 58.5 61.13 62.25 65.63 66.75 68.63
AGP1 (MHz) 48.75 50.63 51 52.13 52.5 53.25 53.63 54.38 48.75 50.63 51.75 53.25 51.38 52.13 52.88 53.25 48.75 49.5 51 51.38 51.75 42.6 43.2 43.8 45 45.9 46.8 48.9 49.8 52.5 53.4 54.9
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
6.1 Register 0: Frequency Select Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description SSEL5 ( Frequency table selection by software via I2C) SSEL4 ( Frequency table selection by software via I2C) SSEL3 ( Frequency table selection by software via I2C) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 (Frequency table selection by software via I2C ) 0 = Selection by hardware 1 = Selection by software I2C - Bit (7:2) 0 = Running 1 = Tristate all outputs
6.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 0 0 1 1 1 1 Pin 27 26 45 46 47 Description CPUCS_C2 free running control 1=can be stopped by CPU_STOP# 0= CPUCS_C2 is free running SDRAM11 (Active / Inactive) 0 = Normal 1 = Spread spectrum enable 0 = 0.25% Center type Spread Spectrum Modulation 1 =0 ~ (-0.5%) Down type Spread Spectrum Modulation SDRAM12 (Active / Inactive) CPUCS_C2(Active / Inactive) CPUCLK1(Active / Inactive) CPUCLK0(Active / Inactive)
6.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 17 16 13 12 11 10 9 8 AGPCLK1(Active / Inactive) AGPCLK0(Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
6.4 Register 3: SDRAM Clock Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 33 34 36 37 38 40 41 42 Description SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive)
6.5 Register 4: PCI Clock Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp X X X X X 1 1 1 Pin 28 30 31 AGPSEL# FS3# FS2# FS1# FS0# SDRAM10 (Active / Inactive) SDRAM9 (Active / Inactive) SDRAM8 (Active / Inactive) Description
6.6 Register 5: Skew Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 1 Pin 21 20 Description CSkew2 (SDRAM to CPU skew program bit) CSkew1 (SDRAM to CPU skew program bit) CSkew0 (SDRAM to CPU skew program bit) CAkew2 (AGP to CPU skew program bit) CAkew1 (AGP to CPU skew program bit) CAkew0 (AGP to CPU skew program bit) 24_48MHz(Active / Inactive) 48MHz(Active / Inactive)
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
6.7 Register 6: Watchdog Timer Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 X 0 0 0 0 0 0 Pin Description Enable Count 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0
6.8 Register 7: M/N Program Register and Divisor
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 0 0 0 0 0 Pin N value bit 8 Test 1 (Internal test use) Test 0 (Internal test use) M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 Description
6.9 Register 8: M/N Program Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 Description
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
6.10 Register 9: Divisor Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count 0 Description
6.11 Register 10: Divisor Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 X X X X X X X Pin Description 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M Ratio SEL3 (See ratio selection table) Ratio SEL2 (See ratio selection table) Ratio SEL1 (See ratio selection table) Ratio SEL0 (See ratio selection table) AGP Ratio SEL2 (See ratio selection table1) AGP Ratio SEL1 (See ratio selection table1) AGP Ratio SEL0 (See ratio selection table1)
6.12 Register 11: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 1 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID
(Read Only)
Description
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
6.13 Register 12: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 0 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Version ID Version ID Version ID Version ID
(Read Only)
Description
RATIO SELECTION TABLE
Reg10 Reg10 Reg10 Reg10 VCO/ VCO/ VCO/ bit6 bit5 bit4 bit3 CPU SDRAM PCI SSEL3 SSEL2 SSEL1 SSEL0 ratio ratio ratio 0 0 0 0 2 2 10 0 0 0 1 2 3 10 0 0 1 0 3 2 10 0 0 1 1 3 3 10 0 1 0 0 3 3 12 0 1 0 1 3 3 16 0 1 1 0 3 4 12 0 1 1 1 3 4 16 1 0 0 0 4 3 10 1 0 0 1 4 3 12 1 0 1 0 4 3 16 1 0 1 1 4 4 12 1 1 0 0 4 6 12 1 1 0 1 6 3 12 1 1 1 0 6 4 12 1 1 1 1 6 6 12
Ratio Selection Table 1 Reg10 Reg10 Reg10 bit2 0 0 0 0 1 1 1 1 bit1 0 0 1 1 0 0 1 1 bit0 0 1 0 1 0 1 0 1 VCO/AG P ratio 3 5 6 8 4 10
AGP2 AGP1 AGP0
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
7.0 ORDERING INFORMATION
Part Number W83194BR-63S Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
8.0 HOW TO READ THE TOP MARKING
W83194BR-63S 28051234 002GAB
1st line: Winbond logo and the type number: W83194BR-63S 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 002: packages made in '00, week 02 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Oct. 2000 Revision 1.0
W83194BR-63S
9.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: Oct. 2000 Revision 1.0

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